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 【知名外企高薪诚聘】Sr. ASIC Design verification Engineer---上海 |
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doudouha
头衔: 海归少校
加入时间: 2008/03/20
文章: 30
海归分: 11718
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作者：doudouha 在 海归招聘 发贴, 来自【海归网】 http://www.haiguinet.com
PREFERRED EXPERIENCE:
- Create detailed specifications of UVD IP and performance test plan.
- Perform UVD integration and verification at chip level.
- Develop or adapt test libraries, emulation model, and test cases from UVD core.
- Develop Verilog and C++ bus functional models for product specific features.
- Design and implement test benches in Verilog, C/C++.
- Develop or adapt, and verify UVD performance test at chip level.
- Work with ASIC design team to debug test failures at IP and chip level.
DEsc<x>riptION OF DUTIES IN ADDITION TO THOSE IN JOB DEsc<x>riptION:
- Minimum BSEE/CE, or equivalent degree.
- 5+ years of hands-on design verification experience in ASIC product development.
- Strong C/C++ software development experience.
- Experience in Verilog, sc<x>ripting experience (csh, perl, awk, etc.).
- SystemC, Vera, and Specman are good assets.
- Knowledge of video codec or processing is preferred.
- Strong problem solving skills, and attention to details.
- Good interpersonal skills (verbal and written).
- An organized, enthusiastic self-starter, strong interest in hardware verification
methodologies.
- Capable of working as an independent contributor and team member.
工作地点：上海
有意者，请尽快与我联系：
Mail:[email protected]
MSN:[email protected]
作者：doudouha 在 海归招聘 发贴, 来自【海归网】 http://www.haiguinet.com
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 【知名外企高薪诚聘】Sr. ASIC Design verification Engineer---上海 -- doudouha - (1317 Byte) 2008-5-27 周二, 18:37 (935 reads)
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